1. Field of the Invention
The invention relates to a semiconductor device and a method for manufacturing the same and, specifically, to a semiconductor device wherein an electric field concentration at a trench bottom portion of the outermost periphery of an operating area is relieved and a deterioration in high voltage strength is suppressed, and a method for manufacturing the same.
2. Description of Related Art
A conventional semiconductor device is shown in FIG. 12 using a trench-type N-channel power MOSFET (Metal Oxide Semiconductor Field Effect transistor) as an example.
On an N+ type silicon semiconductor substrate 21, a drain region 22 formed of an Nxe2x88x92 type epitaxial layer is provided, and on the surface thereof, a P type channel layer 24 is provided. The channel layer 24 has a uniform forming depth across the entire surface of an operating area of the device, and on a peripheral end portion of the channel layer 24 outside the operating area, a P+ type region 24a for securing a high voltage strength is provided.
A trench 27 which penetrates through the channel layer 24 and reaches the drain region 22 is provided, the inner wall of the trench 27 is coated with a gate oxide film 31, and a gate electrode 33 made of polysilicon filled in the trench 27 is provided. On the channel layer surface adjacent to the trench 27, an N+ type source region 35 is formed, and on the channel layer surface between two adjacent cells of such source regions 35, a P+ type body contact region 34 is provided. Furthermore, on the channel layer 24, a channel region (not shown) is formed, extending from the source region 35, along the trench region 27. The top of the gate electrode 33 is covered with an interlayer insulating film 36, and a source electrode 37 which makes contact with the source regions 35 and body contact regions 34 is provided.
Referring to FIG. 13 to FIG. 18, a conventional method for manufacturing a semiconductor device is shown using the trench-type N-channel power MOSFET as an example.
As shown in FIG. 13, an Nxe2x88x92 type epitaxial layer is formed to become a drain region 22 on an N+ type silicon semiconductor substrate 21. Into a peripheral end portion of a predetermined channel layer 24 outside an operating area, a P type impurity of a high concentration is doped and diffused to form a P+ type region 24a (not shown in FIGS. 13-18). Furthermore, an impurity such as boron is doped with a dosage in the order of 1013 into the entire surface and is then diffused to form a P type channel layer 24.
FIGS. 14 and 15 show steps for forming trenches are shown.
In FIG. 14, by a CVD (Chemical Vapor Deposition) method, an NSG (non-doped silicate glass) CVD oxide film 25 is created with a thickness of several thousand xc3x85 on the entire surface. Using a mask made of a resist film formed on the oxide film except the portions to become trench aperture portions 26, the CVD oxide film 25 is partially removed by dry etching so that the trench aperture portions 26 where channel regions 24 are exposed are formed.
In FIG. 15, using the CVD oxide film 25 as a mask, the silicon semiconductor substrate under the trench aperture portions 26 is dry-etched by a CF gas and an HBr gas to form trenches 27 having a depth to penetrate through the channel layer 24 and reach the drain region 22.
In FIG. 16, as dummy oxidation, an oxide film (not shown) is formed on the inner walls of the trenches 27 and the surface of the channel layer 24 to remove etching damage during the dry etching. Thereafter, this dummy oxide film and the CVD oxide film 25 are removed by etching. Then, a gate oxide film 31 is formed. Namely, by applying thermal oxidation to the entire surface, a gate oxide film 31 is formed with, for example, a thickness of approximately several hundred xc3x85.
In FIG. 17, gate electrodes 33, which fill the inside of the trenches 27, are formed. Namely, a non-doped polysilicon layer 32 is deposited on the entire surface including the trenches, and phosphorus is doped and diffused at a high concentration so as to realize a high conductivity. Thereafter, the polysilicon layer adhered to the entire surface is dry-etched without a mask so that the gate electrodes 33 filling the trenches 27 are left.
In FIG. 18, by use of a mask made of a resist film, boron is selectively ion-implanted with a dosage in the order of 1015 to form P+ type body regions 34, and then the resist film is removed.
Thereafter, while masking is provided by a new resist film so as to expose predetermined source regions 35 and gate electrodes 33, arsenic is ion-implanted with a dosage in the order of 1015 to form N+ type source regions 35 on the channel layer surface adjacent to the trenches 27, and then the resist film is removed.
Furthermore, a BPSG (boron phosphorous silicate glass) layer is deposited on the entire surface by a CVD method so that an interlayer insulating film 36 is formed. Thereafter, by use of a resist layer as a mask, the interlayer insulating film 36 is removed except at least the portions on the gate electrodes 33. Thereafter, aluminum is deposited on the entire surface by a sputtering device to form a source electrode 37 which makes contact with the source regions 35 and body contact regions 34.
In this trench-type high-voltage MOSFET, when a drive voltage equal to or higher than a threshold voltage is applied to the gate electrode, providing that a power supply voltage is applied the source electrode and the drain electrode with the drain electrode receiving a positive voltage, a channel region is formed in the channel layer along the trench, and an electric current flows through the channel region. In this manner, the MOSFET is turned on.
On the other hand, if the drive voltage is less than a threshold voltage, the MOSFET is turned off.
In this conventional trench-type high-voltage MOSFET, when the device is turned off, a depletion layer spreads as shown by the broken lines in FIG. 12 from a PN junction, under a reverse bias, at the interface between the channel layer 24 and drain region 22. This works as a depletion layer when a drive voltage V0 is applied. Since the Nxe2x88x92 epitaxial layer of the drain region 22 is low in impurity concentration compared to the P type channel layer 24, the depletion layer mostly extends in the direction of the drain region 22 and retains a drain voltage.
In this configuration, compared to the bottom edge of the trench 27 in the actual operation area, the bottom edge of the outermost peripheral trench 27a has a greater electric field intensity, therefore, an electric field concentration occurs in this region, as described below.
First, an electric field intensity E of the bottom edge of each trench is given by the following equation:
E=V0/d
In the above equation, d is a distance from the bottom edge of each trench to the closest drain region side depletion layer edge. As shown in FIG. 12, this value is d11 for the outermost peripheral trench 27a, and d12 for the trench 27 in the operating area.
In addition, the depletion layer which spreads to the drain region 22 is continuous, whereas the depletion layer which spreads to the channel layer 24 is separated into isolated portions by the trenches, which do not allow formation of the depletion layer inside thereof because of the insulating layer. In the operating area, since the trenches 27 provides isolation and, also, the impurity concentration of the channel layer 24 is higher than the impurity concentration of the drain region 22, the depletion layer spreads toward the channel layer side to a lesser extent and than the drain region side. On the other hand, outside of the outermost peripheral trench 27a, there is a sufficient distance to the P+ region and no restriction due to trenches 27 on the channel layer side. Therefore, the depletion layer spreads to a greater extent toward to the channel layer side than in the operating area. Furthermore, for a fixed applied voltage V0, the width d0 of the depletion layer at its widest portion is almost equal regardless its location, i.e., the inside of the operating area and periphery thereof.
That is, outside of the outermost peripheral trench 27a, the depletion layer in the channel layer side easily spreads and, accordingly, the spread of the depletion layer toward the drain region side becomes less than that of the inside of the operating area. Consequently, the distance from the bottom edge of the trench to the depletion layer edge becomes narrower than that of the trench 27 (d12 greater than d11). In this configuration, inside the operating area, the trenches 27 are arranged at even intervals and the depletion layer evenly spreads accordingly. Therefore, the distance d is shorter only at the outermost peripheral trench 27a. 
Thus, the electric field intensity E of the trench has a greatest value at the outermost peripheral trench 27a, and an electric field concentration occurs in this location.
This leads to a reduction in the high voltage strength between the drain and the source. In a case of an IGBT (Insulated Gate Bipolar Transistor), the pertinent portion is between the collector and emitter. At a high temperature, the high voltage strength may become less than the allowable maximum high voltage.
For example, a characteristic diagram showing a collector-emitter voltage (VCES) as a function of a temperature (Ta) is shown in FIG. 19. According to this diagram, at an ambient temperature of 75xc2x0 C. or higher, the VCES value is low due to an electric field concentration, resulting in negative temperature characteristics. Therefore, there has been a major problem in deterioration in high voltage strength between the collector and emitter due to an electric field concentration.
The invention provides a semiconductor device including an operating area, a plurality of first trench-type transistors provided in the outermost peripheral of the operating area, and a plurality of second trench-type transistors provided in the operating area inside the outermost peripheral. In this configuration, a trench depth of the first trench-type transistors is shorter than a trench depth of the second trench-type transistors.
The invention also provides a method for manufacturing a semiconductor device. The method includes preparing a mask having a first aperture and a second aperture. The first and second apertures have different aperture sizes. The method also includes providing a semiconductor substrate and forming a first trench and a second trench in the semiconductor substrate using the mask in one process step.
The invention further provides another method for manufacturing a semiconductor device. The method includes forming a region of a first conduction type on a semiconductor substrate of a second conduction type, and forming a plurality of first trenches in an outermost peripheral of a predetermined area of the semiconductor substrate and a plurality of second trenches in the predetermined area inside the outermost peripheral. The first trenches have a depth shorter than the second trenches. The predetermined area corresponds to an operating area of the semiconductor device. The method also includes forming insulating films on inner surfaces of the first and second trenches, filling the first and second trenches with a semiconductor material to form electrodes, and forming regions of the second conduction type in a surface of the region of the first conduction type. Each of the regions of the second conduction type is adjacent one of the first and second trenches. In this configuration, the region of a first conduction type may be a channel layer and a surface of the semiconductor substrate may serve as a drain region of the semiconductor device. Furthermore, the regions of the second conductivity type may be source regions.
The invention also provides a method for manufacturing a semiconductor device. The method includes preparing a mask having a first aperture, a second aperture and a third aperture. Each of the first, second and third apertures has a different aperture size. The method further includes providing a semiconductor substrate, and forming a first trench, a second trench and a third trench in the semiconductor substrate using the mask in one process step.
The invention further provides another method for manufacturing a semiconductor device. The method includes forming a region of a first conduction type on a semiconductor substrate of a second conduction type, and forming a plurality of first trenches in an outermost peripheral of a predetermined area of the semiconductor substrate, a plurality of second trenches in the predetermined area inside the first trenches and a plurality of third trenches in the predetermined area inside the second trenches. The second trenches having a depth shorter than the third trenches and longer than the first trenches. The predetermined area corresponds to an operating area of the semiconductor device. The method also includes forming insulating films on inner surfaces of the first, second and third trenches, filling the first, second and third trenches with a semiconductor material to form electrodes, and forming regions of the second conduction type in a surface of the region of the first conduction type. Each of the regions of the second conduction type is adjacent one of the first second and third trenches. In this configuration, the region of a first conduction type may be a channel layer and a surface of the semiconductor substrate may serve as a drain region of the semiconductor device. Furthermore, the regions of the second conductivity type may be source regions.